1. Field of the Invention
The present invention relates to a method of correcting an error code generated during an operation of a successive approximation register analog-digital converter (SAR ADC), and more specifically, to an SAR ADC having a wide dynamic operation range and a high signal-to-noise ratio.
2. Discussion of Related Art
In recent years, successive approximation register analog-digital converters (SAR ADCs) having a resolution of 8 to 16 bits and a conversion speed of 5 to 100 MS/s have drawn attention. Furthermore, the SAR ADCs are emerging as a candidate for a next generation high efficiency data converter due to low power consumption. Despite these advantages of the SAR ADC, since these SAR ADCs use a method of finding a digital output value as close as possible to an input by fixing the input and sequentially varying a reference voltage, there is no method of correcting errors generated during the operation. Due to characteristics of the SAR ADC, most SAR DAC circuits have used a digital error correction method.
There is a method of correcting an error of a conventional SAR ADC through an algorithm using multiple components including a capacitor array consisting of RN (R<2), a linear feedback shift register (LFSR), a memory, a comparison bit generator, etc. However, when the error of the SAR ADC is corrected through the above method, a capacitor mismatch characteristic is degraded by a non-binary capacitor array, and it is difficult to embody the SAR ADC due to the complicated correction algorithm.
Further, conventional SAR ADCs dispose one redundant bit and correct an error generated in an upper code of the redundant bit. However, although the error correction method using the redundant bit can correct the error in the upper code of the redundant bit, it is impossible to correct an error in a lower code of the redundant bit. Accordingly, there is a demand for circuit techniques compensating for this problem.